As the size of integrated circuits is reduced and the number of integrated circuits on a chip increases, the components that make up the circuits must be positioned closer together in order to comply with the limited space available on a typical chip. Current research, therefore, is directed towards achieving a greater density of active components per unit area of a semiconductor substrate. In addition, the components must be oriented vertically by either building the devices up from the substrate surface or by burying the devices in trenches formed within the face of the semiconductor body. A trench capacitor, for example, has been used in dynamic random access memory (DRAM) cells and other circuits to try to further reduce the overall area of such devices.
A problem associated with semiconductor processing typically involves smearing of the materials over the trench regions during polishing. In particular, after trenches are filled, it is necessary to selectively remove layers of material from the “field” regions between each trench of the semiconductor substrate to achieve a highly planar surface topography. A highly planar surface topography is sought because it reduces both the potential for current leakage (i.e., short-circuiting) between active regions of the integrated circuit and the potential for depth of focus lithography problems during subsequent interconnect processing steps. However, during polishing, materials can be undesirably smeared over portions of the substrate surface, sometimes partially or wholly covering the trench regions, making subsequent wafer processing difficult. Accordingly, control of the smearing of materials over the trench regions following planarization or polishing processes is important for ensuring optimum semiconductor performance.
Attempts to solve the problem of providing a highly planarized integrated circuit structure, after having formed trench regions in the substrate, have resulted in a number of planarization schemes. Conventional planarization schemes include, for example, chemical mechanical polishing (CMP), use of permanent spin-on-glass (SOG), and sacrificial etchback SOG. Most conventional schemes, however, do not provide consistent desired results. Indeed, scratching, dishing, comer erosion, and/or smearing are common imperfections associated with many CMP processes when subsequent interconnect processing steps are required.
Thus, there remains a need for improved polishing methods, particularly methods that can reduce in-trench smearing during polishing. The present invention seeks to provide such a method. These and other advantages of the present invention will be apparent from the description of the invention provided herein.